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| M66310P/FP 16-Bit LED Driver with Shift Register and Latch REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Description M66310P/FP is a LED array driver having a 16 bit serial-input and parallel output shift-register function with direct coupled reset input and output latch function. This product guarantees the output electric current of 24 mA which is sufficient for cathode common LED drive, capable of flowing 16 bits continuously at the same time. Parallel output is open drain output. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures the realization of an easy printed circuit. Features * Cathode common LED drive * High output current all parallel output IOH = -24 mA simultaneous lighting available * Low power dissipation: 100 W/package (max) (VCC = 5 V, Ta = 25C, quiescent state) * High noise margin schmitt input circuit provides responsiveness to a long line length. * Equipped with direct-coupled reset * Open drain output (except serial data output) * Wide operating temperature range: Ta = -40 to +85C * Pin layout facilitates printed circuit wiring. (This layout facilitates cascade connection and LED connection.) Application LED array drive of BUTTON TELEPHONE LED array drive of ERASER of a PPC copier Other various LED modules REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 1 of 9 M66310P/FP Logic Diagram Parallel data outputs QA 1 QB 2 QC 24 QD 23 QE 22 QF 21 QG 20 QH 19 QI 18 QJ 17 QK 16 QL 15 QM 14 QN 13 QO 11 QP 12 Serial data output SQP VCC 10 3 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 0 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 1 CK DR 5 4 8 7 6 9 A OE Enable Serial input data input VCC Parallel data output VCC Serial data output CKS CKL GND R Shift Direct Latch clock reset clock input input input Output format Pin Arrangement M66310P/FP Parallel data outputs QA 1 QB 2 VCC 3 QA QB QC QD QE 24 QC 23 QD 22 QE 21 QF 20 QG 19 QH 18 QI 17 QJ 16 QK 15 QL 14 QM 13 QN Serial data input Enable input A 4 OE 5 A OE CKL R CKS QF QG QH QI QJ QK Latch clock input CKL 6 Direct reset input R 7 Parallel data outputs Shift clock input CKS 8 GND 9 Serial data output SQP 10 Parallel data outputs QO 11 QP 12 SQP QO QP QL QM QN (Top view) Outline: PRDP0024AA-A (24P4D) (24P2N-B) REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 2 of 9 M66310P/FP Functional Description As M66310P/FP uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shift-register consists of two flip-flops having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when "L" changes to "H". Serial data input A is the data input of the first-step shift-register and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is "L", the signal of "L" shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the outputs from QA to QP. Outputs from QA to QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. If CKS and CKL are connected, the state of the shifting register with one clock delay is outputted to QA to QP. When reset input R is changed to "L", QA to QP and SQP are reset. In this case, shifting and latching registers are reset. If "H" is impressed to output enable input OE, QA to QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation. Function Table (Note) Input Operation Mode Reset Shift latch Shift t1 Latch t2 Latch t2 Output disable R L H H H H X CKS CKL X X X X X X X X A X H X L X X OE X L L L L H QA Z H Z Z QB Z qA0 qA0 Z QC Z qB0 qB0 Z QD Z qC0 qC0 Z QE Z qD0 qD0 Z QF Z qE0 qE0 Z Parallel Data Output QG Z qF0 qF0 Z QH Z qG0 qG0 Z QI Z QI0 qH0 QI0 qH0 Z QJ Z qI0 qI0 Z QK Z qJ0 qJ0 Z QL Z qK0 qK0 Z QM Z qL0 qL0 Z QN Z qM0 qM0 Z QO Z qN0 qN0 Z QP Z qO0 qO0 Z Serial Data Output SQP Remarks L qO0 qO0 qP - Output lighting "H" Output lights-out "L" - QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QJ0 QK0 QL0 QM0 QN0 QO0 QP0 qO0 QJ0 QK0 QL0 QM0 QN0 QO0 QP0 qO0 operation Shift t1 Note : Change from low-level to high-level 0 Q : Output state Q before CKL changed X: Irrelevant 0 q : Contents of shift register before CKS changed q: Contents of shift register t1, t2: t2 is set after t1 is set Z: High impedance REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 3 of 9 M66310P/FP Absolute Maximum Ratings (Ta = -40 to +85C, unless otherwise noted) Item Supply voltage Input voltage Output voltage Input protection diode current Output parasitic diode current Output current per output pin Supply/GND current Power dissipation Storage temperature range Note: QA to QP SQP Symbol VCC VI VO IIK IOK IO ICC Pd Tstg Ratings -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -20 20 -20 20 -50 25 -410, +20 500 -65 to +150 Unit V V V mA mA mA mA mW C VCC, GND (Note) Conditions VI < 0 V VI > VCC VO < 0 V VO > VCC M66310FP; Ta = -40 to +70C, Ta = 70 to 85C are derated at -6 mW/C. Recommended Operating Conditions (Ta = -40 to +85C, unless otherwise noted) Item Supply voltage Input voltage Output voltage Operating temperature range Symbol VCC VI VO Topr Min 4.5 0 0 -40 Limits Typ 5 -- -- -- Max 5.5 VCC VCC +85 Unit V V V C REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 4 of 9 M66310P/FP Electrical Characteristics (VCC = 4.5 to 5.5 V, unless otherwise noted) Limits Item Positivegoing threshold voltage Negativegoing threshold voltage High-level output voltage QA to QP High-level output voltage SQP Low-level output voltage SQP High-level input current Low-level input current Maximum output leakage current QA to QP Quiescent supply current Note: Symbol VT+ Min Ta = 25C Typ Max -- 0.7xVCC Ta = -40 to +85C Min Max 0.35xVCC 0.7xVCC Unit V Conditions VO = 0.1V, VCC-0.1V IO = 20 A 0.35xVCC VT- 0.2xVCC -- 0.55xVCC 0.2xVCC 0.55xVCC V VO = 0.1V, VCC-0.1V IO = 20 A VOH VCC-0.1 3.83 3.50 VCC-0.1 3.83 -- -- -- -- -- -- -- -- -- -- VCC-0.1 3.66 3.25 VCC-0.1 3.66 -- -- -- -- -- V VI = VT+, VT- VCC = 4.5 V IOH = -20 A IOH = -24 mA (Note) IOH = -40 mA IOH = -20 A IOH = -4 mA VOH V VI = VT+, VT- VCC = 4.5 V VOL -- -- -- -- 0.1 0.44 -- -- 0.1 0.53 V VI = VT+, VT- VCC = 4.5 V IOL = 20 A IOL = 4 mA IIH -- -- 0.5 -- 5.0 A VI = VCC, VCC = 5.5 V IIL -- -- -0.5 -- -5.0 A VI = GND, VCC = 5.5 V IO -- -- -- -- 1.0 -1.0 -- -- 10.0 -10.0 A VI = VT+, VT- VCC = 5.5 V VO = VCC VO = GND ICC -- -- 20.0 -- 200.0 A VI = VCC, GND, VCC = 5.5 V M66310 is used under the condition of an output current IOH = -40 mA, the number of simultaneous drive outputs are restricted as shown in the Duty Cycle-IOH of Standard characteristics. REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 5 of 9 M66310P/FP Switching Characteristics (VCC = 5V) Limits Item Maximum clock frequency Low-level to high-level and high-level to low-level output propagation time (CKS-SQP) High-level to low-level output propagation time (RSQP) High-level to low-level output propagation time (RQA to QP) Low-level to high-level and high-level to low-level output propagation time (CKL-QA to QP) Output enable time to lowlevel and high-level (OE-QA to QP) Input Capacitance Output Capacitance Power dissipation (Note 1) Capacitance Note: Symbol fmax tPLH tPHL Min 5 -- -- Ta = 25C Typ -- -- -- Max -- 100 100 Ta = -40 to +85C Min Max 4 -- -- -- 130 130 Unit MHz ns ns Conditions CL = 50 pF RL = 1 k (Note 2) tPHL -- -- 100 -- 130 ns tPHZ -- -- 150 -- 200 ns tPZH tPHZ -- -- -- -- 100 150 -- -- 130 200 ns ns tPZH tPHZ CI CO CPO -- -- -- -- -- -- -- -- -- 11 100 150 10 15 -- -- -- -- -- -- 130 200 10 15 -- ns ns pF pF pF OE = VCC 1. CPD is the internal capacitance of the IC calculated from operation supply current under no-load conditions. (per latch) The power dissipated during operation under no-load conditions is calculated using the following formula: 2 PD = CPD * VCC * fI + ICC * VCC Timing Requirements (VCC = 5 V) Limits Item CKS, CKL, R pulse width A setup time with respect to CKS CKS setup time with respect to CKL A hold time with respect to CKS R, recovery time with respect to CKS, CKL Symbol tw tsu tsu th trec Min 100 100 100 10 50 Ta = 25C Typ -- Max -- Ta = -40 to +85C Min Max 130 130 130 15 70 -- Unit ns ns ns ns ns Conditions (Note 2) REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 6 of 9 M66310P/FP Note: 2. Test Circuit Input VCC QA to QP PG 50 GND DUT SQP CL CL RL (1) The pulse generator (PG) has the following characteristics (10% to 90%): tr = 6 ns, tf = 6 ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance. Typical Characteristics Duty Cycle vs. IOH (VCC = 4.5 V, Ta = 25C) Duty Cycle vs. IOH (VCC = 4.5 V, Ta = 85C) -50 -40 -50 -40 (1) to (16) IOH (mA) IOH (mA) -30 -20 -10 0 0 20 40 60 80 100 -30 -20 -10 0 0 20 40 60 80 100 Repetition frequency > 10 Hz Numbers in ( ) indicate the number of output circuits that operate simultaneously. Current values are per circuit. Repetition frequency > 10 Hz Numbers in ( ) indicate the number of output circuits that operate simultaneously. Current values are per circuit. (1) to (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Duty Cycle (%) Duty Cycle (%) REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 7 of 9 M66310P/FP Timing Chart tw VCC CKS 50% tPLH 50% 50% tPHL 50% VCC CKL 50% GND VOH GND tPZH VOH QA to QP tPHZ 90% 50% SQP 50% VOL tw VOH VCC R 50% 50% trec QA to QP GND VCC VCC A 50% tsu th 50% CKS tPHL 50% GND VOH 50% GND VCC CKS 50% SQP tPHZ VOL 90% GND QA to QP VOH VCC VCC CKS 50% OE 50% tPZH 50% tPHZ 50% 90% GND tsu tw GND VOH CKL VCC 50% 50% QA to QP GND REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 8 of 9 M66310P/FP Package Dimensions JEITA Package Code P-DIP24-6.3x29.2-2.54 RENESAS Code PRDP0024AA-A Previous Code 24P4D MASS[Typ.] 1.6g 24 13 1 12 c *1 *2 D NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. A2 Reference Dimension in Millimeters Symbol A e SEATING PLANE *3 b3 bp *3 b2 e1 D E A A1 A2 bp b2 b3 c e L 24P2N-B EIAJ Package Code SOP24-P-300-1.27 24 L A1 Plastic 24pin 300mil SOP JEDEC Code -- Weight(g) Lead Material Cu Alloy 13 e e1 E Min Nom Max 7.32 7.62 7.92 29.0 29.2 29.4 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 0.9 1.0 1.3 1.4 1.5 1.8 0.22 0.27 0.34 0 15 2.29 2.54 2.79 3.0 b2 HE E e1 Recommended Mount Pad Symbol F 1 12 A G D A2 e y b A1 x M A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2 c z Z1 Detail G Detail F Dimension in Millimeters Min Nom Max -- -- 2.1 0 0.1 0.2 -- -- 1.8 0.35 0.4 0.5 0.18 0.2 0.25 14.92 15.02 15.12 5.2 5.3 5.4 -- -- 1.27 7.82 8.12 8.42 0.3 0.5 0.7 -- -- 1.41 -- -- 0.525 -- -- 0.675 -- -- 0.25 -- -- 0.1 0 10 -- 0.76 -- -- -- -- 7.62 -- -- 1.27 L1 REJ03F0176-0201 Rev.2.01 Mar 31, 2008 Page 9 of 9 L I2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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